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| (R) EL7457 Data Sheet January 3, 2005 FN7288.3 40MHz Non-Inverting Quad CMOS Driver The EL7457 is a high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 40MHz and features 2A peak drive capability and a nominal onresistance of just 3. The EL7457 is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to ATE pin driving, levelshifting, and clock-driving applications. The EL7457 is capable of running from single or dual power supplies while using ground referenced inputs. Each output can be switched to either the high (VH) or low (VL) supply pins, depending on the related input pin. The inputs are compatible with both 3V and 5V CMOS and TTL logic. The output enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications, where the driver should be disabled during power down. The EL7457 also features very fast rise and fall times which are matched to within 1ns. The propagation delay is also matched between rising and falling edges to within 2ns. The EL7457 is available in 16-pin QSOP, 16-pin SO (0.150"), and 16-pin QFN packages. All are specified for operation over the full -40C to +85C temperature range. Features * Clocking speeds up to 40MHz * 4 channels * 12ns tR/tF at 1000pF CLOAD * 1ns rise and fall time match * 1.5ns prop delay match * Low quiescent current - <1mA * Fast output enable function - 12ns * Wide output voltage range * 8V VL -5V * -2V VH 16.5V * 2A peak drive * 3 on resistance * Input level shifters * TTL/CMOS input-compatible * Pb-free available (RoHS compliant) Applications * CCD drivers * Digital cameras Pinouts EL7457 [16-PIN SO (0.150"), QSOP (0.150")] TOP VIEW 1 INA 2 OE 3 INB 4 VL 5 GND 6 NC 7 INC 8 IND VS+ 16 OUTA 15 OUTB 14 NC 13 VH 12 OUTC 11 OUTD 10 VS- 9 INB 1 VL 2 VL 3 GND 4 INC 5 IND 6 VS- 7 OUTD 8 THERMAL PAD* EL7457 [16-PIN QFN (4x4mm)] TOP VIEW 13 OUTA 14 VS+ 15 INA 16 OE * Pin drivers * Clock/line drivers * Ultrasound transducer drivers * Ultrasonic and RF generators 12 OUTB 11 VH 10 VH 9 OUTC * Level shifting * THERMAL PAD CONNECTED TO PIN 7 (VS-) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL7457 Ordering Information PART NUMBER EL7457CU PACKAGE 16-Pin QSOP (0.150") 16-Pin QSOP (0.150") 16-Pin QSOP (0.150") 16-Pin QSOP (0.150") (Pb-Free) 16-Pin QSOP (0.150") (Pb-Free) 16-Pin QSOP (0.150") (Pb-Free) 16-Pin SO (0.150") 16-Pin SO (0.150") 16-Pin SO (0.150") TAPE & REEL PKG. DWG. # MDP0040 PART NUMBER EL7457CSZ (See Note) EL7457CSZ-T7 (See Note) EL7457CSZ-T13 (See Note) EL7457CL PACKAGE 16-Pin SO (0.150") (Pb-Free) 16-Pin SO (0.150") (Pb-Free) 16-Pin SO (0.150") (Pb-Free) 16-Pin QFN (4x4mm) 16-Pin QFN (4x4mm) 16-Pin QFN (4x4mm) 16-Pin QFN (4x4mm) (Pb-Free) 16-Pin QFN (4x4mm) (Pb-Free) 16-Pin QFN (4x4mm) (Pb-Free) TAPE & REEL PKG. DWG. # MDP0027 EL7457CU-T7 7" MDP0040 7" MDP0027 EL7457CU-T13 13" MDP0040 13" MDP0027 EL7457CUZ (See Note) EL7457CUZ-T7 (See Note) EL7457CUZ-T13 (See Note) EL7457CS - MDP0040 - MDP0046 7" MDP0040 EL7457CL-T7 7" MDP0046 13" MDP0040 EL7457CL-T13 13" MDP0046 - MDP0027 EL7457CLZ (See Note) EL7457CLZ-T7 (See Note) EL7457CLZ-T13 (See Note) - MDP0046 EL7457CS-T7 7" MDP0027 7" MDP0046 EL7457CS-T13 13" MDP0027 13" MDP0046 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2 FN7288.3 January 3, 2005 EL7457 Absolute Maximum Ratings (TA = 25C) Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS+ +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROH ROL ILEAK IPK VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25C, unless otherwise specified. CONDITION MIN TYP MAX UNIT DESCRIPTION Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Capacitance Input Resistance VIL = 0V VIH = 5V 2.0 0.1 10 0.8 0.1 3.5 50 10 V A V A pF M ON Resistance VH to OUTx ON Resistance VL to OUTx Output Leakage Current Peak Output Current IOUT = -100mA IOUT = +100mA VH = VS+, VL = VSSource Sink 4.5 4 0.1 2.0 2.0 6 6 10 A A A POWER SUPPLY IS Power Supply Current Inputs = VS+ 0.5 1.5 mA SWITCHING CHARACTERISTICS tR tF tRF tD+ tDtDD tENABLE tDISABLE Rise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time tD-1 - tD-2 Mismatch Enable Delay Time Disable Delay Time CL = 1000pF CL = 1000pF CL = 1000pF CL = 1000pF CL = 1000pF CL = 1000pF 13.5 13 0.5 12.5 14.5 2 12 12 ns ns ns ns ns ns ns ns 3 FN7288.3 January 3, 2005 EL7457 Electrical Specifications PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROH ROL ILEAK IPK ON Resistance VH to OUT ON Resistance VL to OUT Output Leakage Current Peak Output Current IOUT = -100mA IOUT = +100mA VH = VS+, VL = VSSource Sink POWER SUPPLY IS Power Supply Current Inputs = VS+ 0.8 2 mA 3.5 3 0.1 2.0 2.0 5 5 10 A A A Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Capacitance Input Resistance VIL = 0V 0.1 3.5 50 VIH = 5V 2.4 0.1 10 0.8 10 V A V A pF M VS+ = +15V, VS- = 0V, VH = +15V, VL = 0V, TA = 25C, unless otherwise specified CONDITION MIN TYP MAX UNIT DESCRIPTION SWITCHING CHARACTERISTICS tR tF tRF tD+ tDtDD tENABLE tDISABLE Rise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time tD-1 - tD-2 Mismatch Enable Delay Time Disable Delay Time CL = 1000pF CL = 1000pF CL = 1000pF CL = 1000pF CL = 1000pF CL = 1000pF 11 12 1 11.5 13 1.5 12 12 ns ns ns ns ns ns ns ns 4 FN7288.3 January 3, 2005 EL7457 Typical Performance Curves 1.8 T=25C HIGH LIMIT=2.4V SUPPLY CURRENT (V) 2 T=25C ALL INPUTS=0 INPUT VOLTAGE (V) 1.6 HYSTERESIS 1.6 1.2 1.4 0.8 1.2 LOW LIMIT=0.8V 5 7 10 SUPPLY VOLTAGE (V) 12 15 0.4 ALL INPUTS=VS+ 1 0 5 7 10 SUPPLY VOLTAGE (V) 12 15 FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 25 9 IOUT=100mA 8 T=25C "ON" RESISTANCE () 7 6 5 4 3 2 5 7 10 SUPPLY VOLTAGE (V) 12 15 VL TO OUT VH TO OUT RISE/FALL TIME (ns) 20 tR 15 tF 10 CL=1000pF T=25C 5 7 10 SUPPLY VOLTAGE (V) 12 15 5 FIGURE 3. "ON" RESISTANCE vs SUPPLY VOLTAGE 16 FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE 25 CL=1000pF VS+=15V DELAY TIME (ns) CL=1000pF RISE/FALL TIME (ns) 14 20 12 tF 15 tD1 tD2 10 tR 8 10 6 -50 -25 0 25 50 75 100 125 5 5 7 10 SUPPLY VOLTAGE (V) 12 15 TEMPERATURE (C) FIGURE 5. RISE/FALL TIME vs TEMPERATURE FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE 5 FN7288.3 January 3, 2005 EL7457 Typical Performance Curves 18 16 DELAY TIME (ns) 14 12 10 8 6 -50 tD1 CL=1000pF VS+=15V RISE/FALL TIME (ns) (Continued) 140 120 VS+=15V tD2 100 80 60 40 20 tF tR -25 0 25 50 75 100 125 0 100 470 1K 2.2K 4.7K 10K TEMPERATURE (C) LOAD CAPACITANCE (pF) FIGURE 7. PROPAGATION DELAY vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 12 POWER DISSIPATION (W) SUPPLY CURRENT (mA) VS+=VH=10V VS-=VL=0V 10 f=100kHz 8 6 4 2 0 100 1.2 1 0.8 909mW 667mW SO16 (0.150") JA=110C/W QFN16 JA=150C/W 0.6 633mW 0.4 QSOP16 (0.150") JA=158C/W 0.2 0 1K LOAD CAPACITANCE (pF) 10K 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs CAPACITIVE LOAD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 2.500W QFN16 JA=40C/W SO16 (0.150") JA=80C/W FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 3 POWER DISSIPATION (W) 2.5 2 1.5 1.250W 1 893mW 0.5 0 QSOP16 (0.150") JA=112C/W 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 6 FN7288.3 January 3, 2005 EL7457 TABLE 1. NOMINAL OPERATING VOLTAGE RANGE PIN VS+ to VSVS- to GND VH VL VH to VL VL to VSMIN 5V -5V VS- + 2.5V VS0V 0V MAX 16.5V 0V VS+ VS+ 16.5V 8V OUTPUT INPUT Timing Diagram 5V 2.5V 0 90% 10% t D+ tR tDtF Standard Test Configuration (CS/CU) VS+ 0.1F VS+ 10k INA EN INB VL 4.7F 1 2 3 4 0.1F 5 6 INC IND 7 8 12 11 1000pF 10 9 1000pF OUTD OUTC 16 1000pF 15 14 1000pF 13 0.1F VH 4.7F OUTB OUTA 4.7F VS0.1F 4.7F 7 FN7288.3 January 3, 2005 EL7457 Pin Descriptions 16-PIN QSOP (0.150"), SO (0.150") 1 16-PIN QFN (4x4mm) 15 NAME INA FUNCTION Input channel A VS+ EQUIVALENT CIRCUIT VS+ INPUT VS- VS- CIRCUIT 1 2 3 4 5 6, 13 7 8 9 10 16 1 2, 3 4 OE INB VL GND NC Output Enable Input channel B Low voltage input pin Input logic ground No connection Input channel C Input channel D Negative supply voltage Output channel D (Reference Circuit 1) (Reference Circuit 1) 5 6 7 8 INC IND VSOUTD (Reference Circuit 1) (Reference Circuit 1) VH VS+ OUTPUT VSVSVL CIRCUIT 2 11 12 14 15 16 9 10, 11 12 13 14 OUTC VH OUTB OUTA VS+ Output channel C High voltage input pin Output channel B Output channel A Positive supply voltage (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 2) 8 FN7288.3 January 3, 2005 EL7457 Block Diagram OE VS+ VH INPUT GND LEVEL SHIFTER 3-STATE CONTROL OUTPUT VSVL Applications Information Product Description The EL7457 is a high performance 40MHz high speed quad driver. Each channel of the EL7457 consists of a single Pchannel high side driver and a single N-channel low side driver. These 3 devices will pull the output (OUTX) to either the high or low voltage, on VH and VL respectively, depending on the input logic signal (INX). It should be noted that there is only one set of high and low voltage pins. A common output enable (OE) pin is available on the EL7457. This pin, when pulled low will put all outputs in to the high impedance state. The EL7457 is available in 16-pin SO (0.150"), 16-pin QSOP, and ultra-small 16-pin QFN packages. The relevant package should be chosen depending on the calculated power dissipation. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL7457 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated: 4 PD = ( V S x I S ) + 2 ( CINT x VS x f ) + ( CL x VOUT x f ) 1 2 where: VS is the total power supply to the EL7457 (from VS+ to VS-) VOUT is the swing on the output (VH - VL) CL is the load capacitance CINT is the internal load capacitance (80pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application's power dissipation, the maximum junction temperature can be calculated: T JMAX = T MAX + JA x PD Supply Voltage Range and Input Compatibility The EL7457 is designed for operation on supplies from 5V to 15V with 10% tolerance (i.e. 4.5V to 18V). The table on page 6 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. The EL7457 does not contain a true analog switch and therefore VL should always be less than VH. All input pins are compatible with both 3V and 5V CMOS signals With a positive supply (VS+) of 5V, the EL7457 is also compatible with TTL inputs. Power Supply Bypassing When using the EL7457, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7457 necessitate the use of a bypass capacitor on both the positive and negative supplies. It is recommended that a 4.7F tantalum capacitor be used in parallel with a 0.1F low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7457 is driving highly capacitive loads. 9 where: TJMAX is the maximum junction temperature (125C) TMAX is the maximum ambient operating temperature PD is the power dissipation calculated above JA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves on page 6. FN7288.3 January 3, 2005 EL7457 QSOP Package Outline Drawing 10 FN7288.3 January 3, 2005 EL7457 SO Package Outline Drawing 11 FN7288.3 January 3, 2005 EL7457 QFN Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7288.3 January 3, 2005 |
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